(1) Field of the Invention
The present invention relates to the manufacturing of semiconductor memories, and in particular, directed to a stacked-gate flash memory having a shallow trench isolation with a high step and high lateral coupling and to a method of forming the same.
(2) Description of the Related Art
One of the thrusts in trying to gain programming and erase speeds in stacked-gate flash memories is to increase the coupling ratios. Thinner inter-poly oxides can indeed support higher coupling ratios between the word line and the floating gate, however, data retention becomes a concern due to leakages. Furthermore, word line voltages have been increased to increase programming and erase speeds. But, without the supporting larger area, which is provided in this invention, the situation has exacerbated the well-known problem of junction break-down. It is shown later in the embodiments of this invention that larger area can be achieved between the word line and the floating gate by advantageously introducing a step-up in the shallow trench isolation in a stacked-gate flash memory cell.
The importance of data retention capacity and the coupling ratio in a memory cell has been well recognized since the advent of the one-transistor cell memory cell with one capacitor. Over the years, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improving its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Generally, flash EEPROM cells having both functions of electrical programming and erasing may be classified into two categories, namely, a stack-gate structure and a stacked-gate structure. A conventional stack-gate type cell is shown in FIG. 1 where, as is well known, tunnel oxide film (120), a floating gate (130), an interpoly insulating film (140) and a control gate (150) are sequentially stacked on a silicon substrate (100) between a drain region (113) and a source region (115) separated by channel region (117). Substrate (100) and channel region (117) are of a first conductivity type, and the first (113) and second (115) doped regions are of a second conductivity type that is opposite the first conductivity type.
The programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling mentioned above. Basically, a sufficiently high voltage is applied to control gate (150) and drain (113) while source (115) is grounded to create a flow of electrons in channel region (117) in substrate (100). Some of these electrons gain enough energy to transfer from the substrate to control gate (150) through thin gate oxide layer (120) by means of (F-N) tunneling. The tunneling is achieved by raising the voltage level on control gate (150) to a sufficiently high value of about 12 volts. As the electronic charge builds up on floating gate (130), the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, floating gate (130) remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, floating gate (130) can be erased by grounding control gate (150) and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate.
The thicknesses of the various portions of the oxide layers on the stacked-gate side (between the control gate and the source) and the stacked-side (between the floating gate and the drain) of the memory cell of FIG. 1b play an important role in determining such parameters as current consumption, coupling ratio and the memory erase-write speed, especially in an environment where feature sizes in advanced integrated circuits are being scaled down at a rapid rate. In prior art, various methods have been developed to address these parameters. For example, EPROMs having a trench-like coupling capacitors have been disclosed to address the shrinking area of the gate electrodes, and hence the capacitive coupling ratio between the floating gate and control gates on a conventional prior art EPROM.
In U.S. Pat. No. 5,480,821, Chang discloses a method of fabricating source-coupling, stacked-gate, virtual ground flash EEPROM array where a poly1 floating gate of a cell is formed over a first portion of a channel region in the substrate and is separated from the channel region by a layer of floating gate oxide. Each floating gate includes a tunneling arm that extends over the cell's source line and is separated therefrom by thin tunnel oxide. A poly2 word line is formed over the floating gates of the storage cells in each row of the array. The poly2 word line is separated from the underlying floating gate by a layer of oxide/nitride/oxide ONO. The word lines run perpendicular to the buried n+ bit lines and extend over a second portion of the channel region of each cell in the row to define the internal access transistor of the cell. The word line is separated from the second portion of the channel region by the ONO layer. Chang also discloses the same flash EEPROM array in U.S. Pat. No. 5,412,238 as well as a method for programming the same in U.S. Pat. No. 5,644,532.
Hong, also discloses a stepped floating gate EEPROM device in U.S. Pat. No. 5,569,945 with a high coupling ratio. The fabrication comprises forming a dielectric layer on a substrate and a sacrificial structure on portions of the dielectric layer, forming a first polysilicon layer over the sacrificial structure and other exposed surfaces of the device, patterning the first polysilicon layer and the dielectric layer by masking and etching to form a stepped electrode structure partially upon the sacrificial structure and partially upon the other exposed surfaces of the device, applying ion implantation into the substrate outside of the area covered by the stepped electrode structure, removing the sacrificial layer from the surface of the substrate and from beneath the stepped electrode structure, forming a second layer of dielectric material on the exposed surfaces of the stepped electrode structure and the substrate, and forming a second polysilicon layer over and under overhanging portions the second layer of dielectric material and the substrate.
Sato discloses a nonvolatile semiconductor memory device in which the overlap area of the control gate electrode and the floating gate electrode is increased without increasing the area of the memory cell, and a method of producing the same in U.S. Pat. No. 5,686,333.
Acocella, et al., in U.S. Pat. No. 5,643,813 show improved packing density as well as improved performance and higher manufacturing yields by confining floating gate structures between isolation structures covered with a thin nitride layer.
In the present invention, a method to increase the coupling ratio of word line to floating gate is disclosed. This is accomplished by providing a step-up in the shallow trench isolation in a stacked-gate flash memory cell without any increase in the lateral dimensions of the cell.